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Setup Time and Hold Time

2022-09-23 09:38:43Stepping on the pit record

Created:

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As shown in the figure above: when the data data passes through T_co+T_comb and reaches the d2 end (when the green color is cut off), there is still a distance (white) from the setup time period before the rising edge of D2_clk2, and the setup time meets

  • T_skew: The difference between the clock clk arriving at the D2 clock terminal and reaching the D1 clock terminal (orange)
  • T_co: The time when data passes through a trigger and reaches the Q terminal
  • T_comb: The time elapsed between Q1 and d2 for combinatorial logic

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As shown in the figure above: when the data data passes through T_co+T_comb and reaches the d2 end (when the green color is cut off), it is already in the setup time period before the rising edge of D2_clk2, and the setup time is not satisfied

The solution is shown in the lower right corner of the picture above:

  • Reducing the frequency affects the chip specification, so it is generally not used
  • The front-end design can operate the T_comb duration, that is, adjust the combinational circuit, such as placing the decoding address after the D2 flip-flop
  • Backend can operate layout and routing
  • Process determines T_co and T_setup

Hold Time:

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After D2 processes the old data sent by D1 at time T1, the new data sent by D1 at time T2 still exists:
T_co + T_comb


Summary

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  • setup time is for the Capture edge, the data to be transmitted cannot come too late
  • hold time is for the Capture edge, new data cannot come too early to ensure that the data to be transmitted is kept for a period of time
  • Compared to Capture edge, the data to be transmitted must come early (setup time) and leave late (hold time)

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